/*
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/

/**********************************************************************************************************************
 * File Name    : intc_gic_iobitmask.h
 * Version      : 1.00
 * Description  : IO bit mask file for intc_gic.
 *********************************************************************************************************************/

#ifndef INTC_GIC_IOBITMASK_H
#define INTC_GIC_IOBITMASK_H

#define R_INTC_GIC_GICC_ICCICR_EN_Msk             (0x00000001UL)
#define R_INTC_GIC_GICC_ICCICR_EN_Pos             (0UL)
#define R_INTC_GIC_GICC_ICCPMR_P_Msk              (0x000000FFUL)
#define R_INTC_GIC_GICC_ICCPMR_P_Pos              (0UL)
#define R_INTC_GIC_GICC_ICCBPR_BP_Msk             (0x00000007UL)
#define R_INTC_GIC_GICC_ICCBPR_BP_Pos             (0UL)
#define R_INTC_GIC_GICC_ICCIAR_ACKINTID_Msk       (0x000003FFUL)
#define R_INTC_GIC_GICC_ICCIAR_ACKINTID_Pos       (0UL)
#define R_INTC_GIC_GICC_ICCIAR_CPUID_Msk          (0x00001C00UL)
#define R_INTC_GIC_GICC_ICCIAR_CPUID_Pos          (10UL)
#define R_INTC_GIC_GICC_ICCEOIR_EOIINTID_Msk      (0x000003FFUL)
#define R_INTC_GIC_GICC_ICCEOIR_EOIINTID_Pos      (0UL)
#define R_INTC_GIC_GICC_ICCEOIR_CPUID_Msk         (0x00001C00UL)
#define R_INTC_GIC_GICC_ICCEOIR_CPUID_Pos         (10UL)
#define R_INTC_GIC_GICC_ICCRPR_P_Msk              (0x000000FFUL)
#define R_INTC_GIC_GICC_ICCRPR_P_Pos              (0UL)
#define R_INTC_GIC_GICC_ICCHPIR_PENDINTID_Msk     (0x000003FFUL)
#define R_INTC_GIC_GICC_ICCHPIR_PENDINTID_Pos     (0UL)
#define R_INTC_GIC_GICC_ICCHPIR_CPUID_Msk         (0x00001C00UL)
#define R_INTC_GIC_GICC_ICCHPIR_CPUID_Pos         (10UL)
#define R_INTC_GIC_GICC_ICCIIDR_I_Msk             (0x00000FFFUL)
#define R_INTC_GIC_GICC_ICCIIDR_I_Pos             (0UL)
#define R_INTC_GIC_GICC_ICCIIDR_RN_Msk            (0x0000F000UL)
#define R_INTC_GIC_GICC_ICCIIDR_RN_Pos            (12UL)
#define R_INTC_GIC_GICC_ICCIIDR_AV_Msk            (0x000F0000UL)
#define R_INTC_GIC_GICC_ICCIIDR_AV_Pos            (16UL)
#define R_INTC_GIC_GICC_ICCIIDR_P_Msk             (0xFFF00000UL)
#define R_INTC_GIC_GICC_ICCIIDR_P_Pos             (20UL)
#define R_INTC_GIC_GICD_ICDDCR_EN_Msk             (0x00000001UL)
#define R_INTC_GIC_GICD_ICDDCR_EN_Pos             (0UL)
#define R_INTC_GIC_GICD_ICDICTR_IT_Msk            (0x0000001FUL)
#define R_INTC_GIC_GICD_ICDICTR_IT_Pos            (0UL)
#define R_INTC_GIC_GICD_ICDICTR_CN_Msk            (0x000000E0UL)
#define R_INTC_GIC_GICD_ICDICTR_CN_Pos            (5UL)
#define R_INTC_GIC_GICD_ICDIIDR_IN_Msk            (0x00000FFFUL)
#define R_INTC_GIC_GICD_ICDIIDR_IN_Pos            (0UL)
#define R_INTC_GIC_GICD_ICDIIDR_RN_Msk            (0x00FFF000UL)
#define R_INTC_GIC_GICD_ICDIIDR_RN_Pos            (12UL)
#define R_INTC_GIC_GICD_ICDIIDR_IV_Msk            (0xFF000000UL)
#define R_INTC_GIC_GICD_ICDIIDR_IV_Pos            (24UL)
#define R_INTC_GIC_GICD_ICDISERn_SEB_Msk          (0xFFFFFFFFUL)
#define R_INTC_GIC_GICD_ICDISERn_SEB_Pos          (0UL)
#define R_INTC_GIC_GICD_ICDICERn_CEB_Msk          (0xFFFFFFFFUL)
#define R_INTC_GIC_GICD_ICDICERn_CEB_Pos          (0UL)
#define R_INTC_GIC_GICD_ICDISPRn_CPB_Msk          (0xFFFFFFFFUL)
#define R_INTC_GIC_GICD_ICDISPRn_CPB_Pos          (0UL)
#define R_INTC_GIC_GICD_ICDICPRn_CPB_Msk          (0xFFFFFFFFUL)
#define R_INTC_GIC_GICD_ICDICPRn_CPB_Pos          (0UL)
#define R_INTC_GIC_GICD_ICDABRn_AB_Msk            (0xFFFFFFFFUL)
#define R_INTC_GIC_GICD_ICDABRn_AB_Pos            (0UL)
#define R_INTC_GIC_GICD_ICDIPRn_PBO0_Msk          (0x000000FFUL)
#define R_INTC_GIC_GICD_ICDIPRn_PBO0_Pos          (0UL)
#define R_INTC_GIC_GICD_ICDIPRn_PBO1_Msk          (0x0000FF00UL)
#define R_INTC_GIC_GICD_ICDIPRn_PBO1_Pos          (8UL)
#define R_INTC_GIC_GICD_ICDIPRn_PBO2_Msk          (0x00FF0000UL)
#define R_INTC_GIC_GICD_ICDIPRn_PBO2_Pos          (16UL)
#define R_INTC_GIC_GICD_ICDIPRn_PBO3_Msk          (0xFF000000UL)
#define R_INTC_GIC_GICD_ICDIPRn_PBO3_Pos          (24UL)
#define R_INTC_GIC_GICD_ICDIPTRn_CPU_TBO0_Msk     (0x000000FFUL)
#define R_INTC_GIC_GICD_ICDIPTRn_CPU_TBO0_Pos     (0UL)
#define R_INTC_GIC_GICD_ICDIPTRn_CPU_TBO1_Msk     (0x0000FF00UL)
#define R_INTC_GIC_GICD_ICDIPTRn_CPU_TBO1_Pos     (8UL)
#define R_INTC_GIC_GICD_ICDIPTRn_CPU_TBO2_Msk     (0x00FF0000UL)
#define R_INTC_GIC_GICD_ICDIPTRn_CPU_TBO2_Pos     (16UL)
#define R_INTC_GIC_GICD_ICDIPTRn_CPU_TBO3_Msk     (0xFF000000UL)
#define R_INTC_GIC_GICD_ICDIPTRn_CPU_TBO3_Pos     (24UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON0_Msk     (0x00000003UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON0_Pos     (0UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON1_Msk     (0x0000000CUL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON1_Pos     (2UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON2_Msk     (0x00000030UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON2_Pos     (4UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON3_Msk     (0x000000C0UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON3_Pos     (6UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON4_Msk     (0x00000300UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON4_Pos     (8UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON5_Msk     (0x00000C00UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON5_Pos     (10UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON6_Msk     (0x00003000UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON6_Pos     (12UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON7_Msk     (0x0000C000UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON7_Pos     (14UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON8_Msk     (0x00030000UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON8_Pos     (16UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON9_Msk     (0x000C0000UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON9_Pos     (18UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON10_Msk    (0x00300000UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON10_Pos    (20UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON11_Msk    (0x00C00000UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON11_Pos    (22UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON12_Msk    (0x03000000UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON12_Pos    (24UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON13_Msk    (0x0C000000UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON13_Pos    (26UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON14_Msk    (0x30000000UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON14_Pos    (28UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON15_Msk    (0xC0000000UL)
#define R_INTC_GIC_GICD_ICDICFRn_INT_CON15_Pos    (30UL)
#define R_INTC_GIC_GICD_PPI_PPI0_Msk              (0x00000800UL)
#define R_INTC_GIC_GICD_PPI_PPI0_Pos              (11UL)
#define R_INTC_GIC_GICD_PPI_PPI1_Msk              (0x00001000UL)
#define R_INTC_GIC_GICD_PPI_PPI1_Pos              (12UL)
#define R_INTC_GIC_GICD_PPI_PPI2_Msk              (0x00002000UL)
#define R_INTC_GIC_GICD_PPI_PPI2_Pos              (13UL)
#define R_INTC_GIC_GICD_PPI_PPI3_Msk              (0x00004000UL)
#define R_INTC_GIC_GICD_PPI_PPI3_Pos              (14UL)
#define R_INTC_GIC_GICD_PPI_PPI4_Msk              (0x00008000UL)
#define R_INTC_GIC_GICD_PPI_PPI4_Pos              (15UL)
#define R_INTC_GIC_GICD_SPI_SPI_Msk               (0xFFFFFFFFUL)
#define R_INTC_GIC_GICD_SPI_SPI_Pos               (0UL)
#define R_INTC_GIC_GICD_ICDSGIR_SGIINTID_Msk      (0x0000000FUL)
#define R_INTC_GIC_GICD_ICDSGIR_SGIINTID_Pos      (0UL)
#define R_INTC_GIC_GICD_ICDSGIR_SATT_Msk          (0x00008000UL)
#define R_INTC_GIC_GICD_ICDSGIR_SATT_Pos          (15UL)
#define R_INTC_GIC_GICD_ICDSGIR_CPUTL_Msk         (0x00FF0000UL)
#define R_INTC_GIC_GICD_ICDSGIR_CPUTL_Pos         (16UL)
#define R_INTC_GIC_GICD_ICDSGIR_TLF_Msk           (0x03000000UL)
#define R_INTC_GIC_GICD_ICDSGIR_TLF_Pos           (24UL)
#define R_INTC_GIC_GICD_PIR4_ID_Msk               (0xFFUL)
#define R_INTC_GIC_GICD_PIR4_ID_Pos               (0UL)
#define R_INTC_GIC_GICD_PIR0_ID_Msk               (0xFFUL)
#define R_INTC_GIC_GICD_PIR0_ID_Pos               (0UL)
#define R_INTC_GIC_GICD_PIR1_ID_Msk               (0xFFUL)
#define R_INTC_GIC_GICD_PIR1_ID_Pos               (0UL)
#define R_INTC_GIC_GICD_PIR2_ID_Msk               (0xFFUL)
#define R_INTC_GIC_GICD_PIR2_ID_Pos               (0UL)
#define R_INTC_GIC_GICD_PIR3_ID_Msk               (0xFFUL)
#define R_INTC_GIC_GICD_PIR3_ID_Pos               (0UL)
#define R_INTC_GIC_GICD_CIR0_ID_Msk               (0xFFUL)
#define R_INTC_GIC_GICD_CIR0_ID_Pos               (0UL)
#define R_INTC_GIC_GICD_CIR1_ID_Msk               (0xFFUL)
#define R_INTC_GIC_GICD_CIR1_ID_Pos               (0UL)
#define R_INTC_GIC_GICD_CIR2_ID_Msk               (0xFFUL)
#define R_INTC_GIC_GICD_CIR2_ID_Pos               (0UL)
#define R_INTC_GIC_GICD_CIR3_ID_Msk               (0xFFUL)
#define R_INTC_GIC_GICD_CIR3_ID_Pos               (0UL)

#endif
